1. Field of the Invention
The present invention generally relates to computer architecture.
2. Description of Related Art
Conventional computer architecture typically includes a single bus that couples a microprocessor with memory and Input/Output (I/O) devices. The bus carries a number of electrical signals between the various components of the system. The speed of the signals is somewhat dictated by the length of the bus. High speed signals are difficult to send over long distances, because of the cross inductance between bus lines. Generally speaking, higher frequencies require shorter bus lines.
I/O ports are typically located on a separate card, whereby the signals must travel through connectors and various printed circuit boards to communicate with of the processor. This limits the speed of the bus and degrades the performance of the processor. The bus speed also controls the rate of data transfer between the processor and memory devices. It is generally desirable to have high data rates between the processor and memory. Usually an increase in data rate requires a larger number of pins on the chip. Adding pins enlarges the size of the chip, increasing the cost and complexity of the same. It would therefore be desirable to have a high speed memory bus that would provide a high data rate with a minimal amount of pins. It would also be desirable to have an architecture that would allow such a high speed bus to operate independently of the I/O devices of the system.
Microprocessors are constantly being redesigned to run at faster clock rates. Usually the development of faster CPU devices require the addition of hardware and/or software, so that the existing system can interface with the new processor. This is particularly true for the interface between the processor and the bus, which contains existing I/O devices that run at the slower data rate. Recent systems have incorporated various levels of cache memory to compensate for the slow data rate between the processor and main memory. Additionally, cache requires additional components, thereby increasing the cost and complexity of the system. It would therefore be desirable to have an architecture that would allow faster processors to be installed into existing systems, without having to drastically change the existing hardware and software of the system.
The present invention is a computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of high speed dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus greatly increases the performance between the processor and memory devices. High speed processors can be substituted or added to the system, without drastically modifying the existing memory and bus. High speed I/O devices such as graphic controllers can also be added to the bus to improve the performance of the controller.
The high speed bus may be used with a conventional bus, so that conventional devices (e.g. I/O devices, system ROMs, etc.) can communication with the processor using existing bus protocols. The dual bus arrangement allows high speed data rates between the processor and memory to occur, while slower devices communicate with the processor on the conventional bus. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows data to be transferred between the busses. For example, if the conventional bus is connected to I/O devices, I/O data can be diverted directly to the high speed bus and memory. Conversely if the high speed bus contains an I/O device, the device can communicate with the conventional bus.
The present invention includes means to incorporate cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both the conventional bus and the separate high speed bus.
Therefore it is an object of this invention to provide a high speed low pin bus between a processor and system memory.
It is also an object of this invention to provide a high speed memory bus that allows faster processors to be substituted or added, without changing the bus or memory structure.
It is also an object of this invention to provide a high speed memory bus that can operate with a conventional bus.
It is also an object of this invention to provide a method for allowing I/O devices to be placed on both a high speed bus and a conventional bus.
It is also an object of this invention to provide a cache on a high speed memory bus.
It is also an object of this invention to provide a multiple bus architecture that allows devices on one bus to communicate with devices on the other bus.
It is also an object of this invention to provide a computer architecture that decouples the performance of the CPU to memory path from the CPU to I/O path.